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14.5
Usage Note
When accessing the U memory by the CPU or the DSP, if the cache is on, access must be
performed from space P2 (non-cacheable space). Operation during access from space P0 cannot be
guaranteed. When the cache is off, spaces P0 and P2 can both be used.
14.6
Sleep Mode
In sleep mode, the U memory cannot be accessed by the I bus master module such as DMAC.
14.7
Address Error
When an address error in write access to the U memory occur, the contents of the U memory may
be corrupted.
Section 14 U Memory
Rev. 4.00 Sep. 14, 2005 Page 453 of 982
REJ09B0023-0400
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