Renesas HD6417641 Hardware Manual page 465

32-bit risc microcomputer superh risc engine family / sh7641 series
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Bit
Bit Name
0
DE
Note:
Writing 0 is possible to clear the flag.
*
Initial
Value
R/W
Descriptions
0
R/W
DMA Enable
This bit enabler or disables the DMA transfer. In an
auto request mode, DMA transfer starts by setting the
DE bit and DME bit in DMAOR to 1. In this time, all of
the bits TE, NMIF in DMAOR, and AE must be 0's. In
an external request or peripheral module request, DMA
transfer starts if DMA transfer request is generated by
the devices or peripheral modules after setting the bits
DE and DME to 1. In this case, however, all of the bits
TE, NMIF, and AE must be 0's an in the case of auto
request mode. Clearing the DE bit to 0 can terminate
the DMA transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 415 of 982
REJ09B0023-0400

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