Timer Gate Control Register (Tgcr) - Renesas HD6417641 Hardware Manual

18.3.12 Timer Gate Control Register (TGCR)

TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These
register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Bit Bit Name

7
6 BDC
5 N
4 P
Initial
value R/W Description
1 R Reserved
This bit is always read as 1. The write value should
always be 1.
0 R/W Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
0 R/W Reverse Phase Output (N) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are
on-output.
0: Level output
1: Reset synchronized PWM/complementary PWM
0 R/W Positive Phase Output (P) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while
the positive pin (TIOC3B, TIOC4A, and TIOC4B) are
on-output.
0: Level output
1: Reset synchronized PWM/complementary PWM
Section 18 Multi-Function Timer Pulse Unit (MTU)
output
output
Rev. 4.00 Sep. 14, 2005 Page 559 of 982
REJ09B0023-0400