Figure 18.114 Poe Block Diagram - Renesas HD6417641 Hardware Manual

Section 18 Multi-Function Timer Pulse Unit (MTU)
The POE has input-level detection circuitry and output-level detection circuitry, as shown in the
block diagram of figure 18.114.
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Input level detection circuit
POE3
POE2
POE1
POE0
[Legend]
OCSR: Output level control/status register
ICSR1: Input level control/status register
Rev. 4.00 Sep. 14, 2005 Page 674 of 982
REJ09B0023-0400
Output level
detection circuit
Output level
detection circuit
Output level
detection circuit
OCSR
ICSR1
Falling-edge
detection circuit
Low-level
detection circuit
φ/8 φ/16 φ/128
Devider
pφ

Figure 18.114 POE Block Diagram

Hi-Z request
control signal
Interrupt request