Figure 19.12 Sample Flowchart For Scif Initialization - Renesas HD6417641 Hardware Manual

Figure 19.12 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear TE and RE bits
Set TFRST and RFRST bits
in SCFCR to 1 to clear
After reading BRK, DR,
and ER flags in SCFSR,
write 0 to clear them
Set data transfer format
Set CKE1 and CKE0 bits
in SCSCR (leaving TE, RE, TIE,
and RIE bits cleared to 0)
Set value in SCBRR
1-bit interval elapsed?
Set RTRG1-0 and TTRG1-0 bits
in SCFCR, and clear TFRST
and RFRST bits to 0
Set TE and RE bits in SCSCR
to 1, and set TIE, RIE,

Figure 19.12 Sample Flowchart for SCIF Initialization

in SCSCR to 0
the FIFO buffer
in SCSMR
Wait
Yes
and REIE bits
End of initialization
Section 19 Serial Communication Interface with FIFO (SCIF)
[1] Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
[1]
[2] Set the data transfer format in
SCSMR.
[3]
Set the CKE1 and CKE0 bits.
[4] Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used. Wait at least one
bit interval after this write before
moving to the next step.
[2]
[5] Set the TE or RE bit in SCSCR
to 1. Also set the TEI, RIE, and
REIE bits to enable the TxD,
[3]
RxD, and SCK pins to be used.
When transmitting, the TxD pin
will go to the mark state.
When receiving in clocked
[4]
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCIF_CLK pin
No
at this point.
[5]
Rev. 4.00 Sep. 14, 2005 Page 735 of 982
REJ09B0023-0400