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Renesas HD151TS207SS Specification Sheet
Renesas HD151TS207SS Specification Sheet

Renesas HD151TS207SS Specification Sheet

Mother board clock generator for intel p4+ chipset (springdale)

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HD151TS207SS
Mother Board Clock Generator
for Intel P4+ Chipset (Springdale)
Description
The HD151TS207SS is Intel CK409T type high-performance, low-skew, low-jitter, PC motherboard clock
generator. It is specifically designed for Intel Pentium ® 4+ chipset.
Features
3 differential pairs of current mode control CPU clocks
1 differential pair of Serial Reference Clock (SRC), selectable 100 MHz/200 MHz
6 copies PCI clocks and 3 copies PCIF clocks @3.3V, 33.3 MHz
1 copy PCI clock @3.3 V, selectable 33.3 MHz/25 MHz
1 copy USB clock @3.3 V, selectable 48 MHz/24 MHz
1 copy DOT clock @3.3 V, 48 MHz
4 copies of 3V66 clocks @3.3 V, 66.6 MHz
1 copy of 3V66/VCH clock @3.3 V, selectable 66.6 MHz/48 MHz
2 copies of REF clocks @3.3 V, 14.318 MHz
Power save and clock stop function
2
TM
I
C
serial port programming
Programmable Clock Control (Spread Spectrum Percentage, Clock Output Skew, Slew Rate)
Watchdog timer and reset output
56pin SSOP (300 mils)
2
Note: I
C is a trademark of Philips Corporation.
Pentium is registered trademark of Intel Corporation
Rev.1.00, Apr.25.2003, page 1 of 38
REJ03D0006-0100Z
Preliminary
Rev.1.00
Apr.25.2003

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Summary of Contents for Renesas HD151TS207SS

  • Page 1 Mother Board Clock Generator for Intel P4+ Chipset (Springdale) Description The HD151TS207SS is Intel CK409T type high-performance, low-skew, low-jitter, PC motherboard clock generator. It is specifically designed for Intel Pentium ® 4+ chipset. Features 3 differential pairs of current mode control CPU clocks 1 differential pair of Serial Reference Clock (SRC), selectable 100 MHz/200 MHz 6 copies PCI clocks and 3 copies PCIF clocks @3.3V, 33.3 MHz...
  • Page 2 HD151TS207SS Key Specifications Supply Voltages: VDD = 3.3 V±5% CPU clock cycle to cycle jitter = |125ps| (SSC Disabled) CPU clock group Skew = 100ps 3V66 clock group Skew = 250psmax PCI clock group Skew = 500psmax Rev.1.00, Apr.25.2003, page 2 of 38...
  • Page 3 HD151TS207SS Pin Arrangement REF0 REF1 VDD_REF XTAL_IN XTAL_OUT VSS_REF FS2/PCIF_0 FS4/PCIF_1 PCIF_2 VDD_PCI VSS_PCI MODE/PCI_0 PCI_1 PCI_2 PCI_3 VDD_PCI VSS_PCI SEL100_200/PCI_4 SEL33_25/PCI_5 PCI_6 PWRDWN#/SAFE_F# 3V66_0/RESET# 3V66_1 VDD_3V66 VSS_3V66 3V66_2 3V66_3 SCLK PCI_STOP#, PWRDWN# = 150 k Internal Pull-up Rev.1.00, Apr.25.2003, page 3 of 38...
  • Page 4 HD151TS207SS Pin Descriptions Pin name Type VSS_A Ground VSS_CPU VSS_IREF VSS_SRC VSS_3V66 VSS_PCI 11, 17 VSS_REF VSS_48 VDD_A Power VDD_CPU 42, 48 VDD_SRC VDD_3V66 VDD_PCI 10, 16 VDD_REF VDD_48 REF0 OUTPUT REF1 XTAL_IN INPUT XTAL_OUT OUTPUT FS2/PCIF_[0:1] INPUT/ OUTPUT PCIF_2...
  • Page 5 HD151TS207SS Pin Descriptions (cont.) Pin name Type PWRDWN#/ INPUT SAFE_F# PULL–UP* 3V66_0/RESET# OUTPUT 3V66_[1:3] 23,26, OUTPUT SCLK INPUT PULL-UP* **SEL66_48/ INPUT/ 3V66_4/VCH OUTPUT SDATA IN/OUTPUT PULL-UP* **SEL48_24/ INPUT/ USB_48 OUTPUT FS3/DOT_48 INPUT/ OUTPUT VTT_PWRGD# INPUT PULL-UP* SRC# OUTPUT OUTPUT CPU_[0:2]#...
  • Page 6 HD151TS207SS Block Diagram 3.3 V VDD_48 VSS_48 XTAL 14.318 MHz PWRDWN#/SAFE_F# Input PCI_STOP# Clock VTT_PWRGD# Select TEST_CLK# *MODE *SEL100_200 *SEL66_48 *SEL48_24 *SEL33_25 *FS_4/3/2A/B SCLK SDATA * : Latched Input pin. Rev.1.00, Apr.25.2003, page 6 of 38 3.3 V VDD_A VSS_A 6×...
  • Page 7 HD151TS207SS C Controlled Register Bit Map Byte0 Control Register Description Reserved Reserved Reserved Reserved PCI_Stop Reflects the current value of the external PCI_STOP# pin Reserved FS_B Reflects the value of the FS_B pin sampled on power up FS_A Reflects the value of the...
  • Page 8 HD151TS207SS C Controlled Register Bit Map (cont.) Table3 FS_A and FS_B pin Input level Logic Level Min Voltage 0 (Low) 1 (High) 0.70V Byte1 Control Register Description Allow control of SCR with assertion of PCI_STOP# SRC Output enable Reserved Reserved...
  • Page 9 HD151TS207SS C Controlled Register Bit Map (cont.) Table4 CPU Clock Power Management Truth Table Signal PWRDWN# CPU[2:0] CPU[2:0] CPU[2:0] Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA, Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 )
  • Page 10 HD151TS207SS C Controlled Register Bit Map (cont.) Byte4 Control Register Description USB_48 2x output drive USB_48MHz Output Enable Allow control of PCIF_2 with assertion of PCI_STOP# Allow control of PCIF_1 with assertion of PCI_STOP# Allow control of PCIF_0 with assertion of PCI_STOP#...
  • Page 11 HD151TS207SS C Controlled Register Bit Map (cont.) Byte7 Vendor Identification Register Description Revision Code Bit3 Revision Code Bit2 Revision Code Bit1 Revision Code Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0 Byte8 Read Back Byte Count Register...
  • Page 12 HD151TS207SS C Controlled Register Bit Map (cont.) Byte9 Control Register Description SSC2 Enable Bit SSC1 Enable Bit Clock Frequency Control Bit4 Clock Frequency Control Bit3 Clock Frequency Control Bit2 Clock Frequency Control Bit1 Clock Frequency Control Bit0 Frequency Select Mode Bit Rev.1.00, Apr.25.2003, page 12 of 38...
  • Page 13 HD151TS207SS C Controlled Register Bit Map (cont.) Table6 Clock Frequency Function Table FS_4 FS_3 FS_2 B9[5] B9[4] B9[3] Rev.1.00, Apr.25.2003, page 13 of 38 FS_A FS_B [MHz] [MHz] B9[2] B9[1] 100.02 100.02 200.03 100.02 133.36 100.02 166.69 100.02 200.03 100.02 400.07...
  • Page 14 HD151TS207SS C Controlled Register Bit Map (cont.) Byte10 Control Register Description SSC Spread Select Bit[2:0] Backup of latch Input FS_4 at Power ON Backup of latch Input FS_3 at Power ON Backup of latch Input FS_2 at Power ON Backup of latch Input FS_A at...
  • Page 15 HD151TS207SS C Controlled Register Bit Map (cont.) Byte12 Control Register Description Reserved Reserved Reserved Reserved Reserved PLL1 Output (VCO1) Frequency Control Bit (M1/N1 Divider Control Bit) PLL1 : for SRC/3V66/PCI_PLL PLL1 N1 Divider Control Bit9 PLL1 N1 Divider Control Bit8 Note: 1.
  • Page 16 HD151TS207SS C Controlled Register Bit Map (cont.) Byte14 Control Register Description Reserved PLL1 M1 Divider Control Bit6 PLL1 M1 Divider Control Bit5 PLL1 M1 Divider Control Bit4 PLL1 M1 Divider Control Bit3 PLL1 M1 Divider Control Bit2 PLL1 M1 Divider Control Bit1...
  • Page 17 HD151TS207SS C Controlled Register Bit Map (cont.) Byte16 Control Register Description 3V66 / PCI / PCIF Divider Control Bit3 3V66 / PCI / PCIF Divider Control Bit2 3V66 / PCI / PCIF Divider Control Bit1 3V66 / PCI / PCIF Divider Control...
  • Page 18 HD151TS207SS C Controlled Register Bit Map (cont.) Byte18 Control Register Description VCO2 Frequency Control Bit7 VCO2 Frequency Control Bit6 VCO2 Frequency Control Bit5 VCO2 Frequency Control Bit4 VCO2 Frequency Control Bit3 VCO2 Frequency Control Bit2 VCO2 Frequency Control Bit1 VCO2 Frequency Control Bit0 Note: 1.
  • Page 19 HD151TS207SS C Controlled Register Bit Map (cont.) Byte19 Control Register Description VCO2 Frequency Read Bit15 VCO2 Frequency Read Bit14 VCO2 Frequency Read Bit13 VCO2 Frequency Read Bit12 VCO2 Frequency Read Bit11 VCO2 Frequency Read Bit10 VCO2 Frequency Read Bit9 VCO2 Frequency Read Bit8...
  • Page 20 HD151TS207SS C Controlled Register Bit Map (cont.) Byte22 Control Register Description CPU Frequency Read Bit7 CPU Frequency Read Bit6 CPU Frequency Read Bit5 CPU Frequency Read Bit4 CPU Frequency Read Bit3 CPU Frequency Read Bit2 CPU Frequency Read Bit1 CPU Frequency Read Bit0...
  • Page 21 HD151TS207SS C Controlled Register Bit Map (cont.) Byte24 Control Register Description Reserved PCI_STOP# Stop PCI_6 Control Bit PCI_STOP# Stop PCI_5 Control Bit PCI_STOP# Stop PCI_4 Control Bit PCI_STOP# Stop PCI_3 Control Bit PCI_STOP# Stop PCI_2 Control Bit PCI_STOP# Stop PCI_1...
  • Page 22 HD151TS207SS C Controlled Register Bit Map (cont.) Byte26 Control Register Description PCIF / PCI Clock Skew2 Control Bit3 PCIF / PCI Clock Skew2 Control Bit2 PCIF / PCI Clock Skew2 Control Bit1 PCIF / PCI Clock Skew2 Control Bit0 PCIF / PCI Clock Skew1...
  • Page 23 HD151TS207SS C Controlled Register Bit Map (cont.) Byte28 Control Register Description Reserved PCI_6 Skew Select Bit PCI_5 Skew Select Bit PCI_4 Skew Select Bit PCI_3 Skew Select Bit PCI_2 Skew Select Bit PCI_1 Skew Select Bit PCI_0 Skew Select Bit Note: 1.
  • Page 24 HD151TS207SS Clock Stop Timing Diagram PCI_STOP# Assertion/De-assersion PCI_STOP# PCI_F SRC (Stoppable) SRC (Stoppable) SRC# (Stoppable) PWRDWN# Assertion/De-assersion PWRDWN# CPU (Stoppable) CPU (Stoppable) CPU# (Stoppable) PWRDWN# Functionality PWRDWN# Normal Iref:2 or Float Rev.1.00, Apr.25.2003, page 24 of 38 6 Iref (Controled by Byte2[6])
  • Page 25 1.7 Renesas clock generator will acknowledge (Renesas clock gen. sends “Low”). 1.8 Controller (host) sends data from byte M to byte M+N–1. 1.9 Renesas clock generator will acknowledge each byte one at a time. 1.10 Controller (host) sends a stop bit.
  • Page 26 2.10 Controller (host) will acknowledge. 2.11 Renesas clock generator will send data from byte M to byte M+N–1. 2.12 When Renesas clock generator sends the last byte, controller (host) will not acknowledge. 2.13 Controller (host) sends a stop bit. 1 bit...
  • Page 27 HD151TS207SS Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage *1 Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55°C (in still air) Storage temperature Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
  • Page 28 HD151TS207SS DC Electrical Characteristics / Serial Input Port Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Min Input Low Voltage Input High Voltage Input Current Input capacitance Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
  • Page 29 HD151TS207SS DC Electrical Characteristics CPU/CPU# Clock Ta = 0°C to 70°C, VDD = 3.3 V, Iref = 475 Item Symbol Min Output voltage Output Current Output resistance Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditionaI (nom) is output current(Ioh) shown in below.
  • Page 30 HD151TS207SS DC Electrical Characteristics SRC/SRC# Clock Ta = 0°C to 70°C, VDD = 3.3 V, Iref = 475 Item Symbol Min Output voltage Output Current Output resistance Notes: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions 2.
  • Page 31 HD151TS207SS DC Electrical Characteristics / 3V66 Buffer (CK409T Type5 Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Output Voltage Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
  • Page 32 HD151TS207SS DC Electrical Characteristics / PCI & PCIF Clock (CK409T Type5 Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Output Voltage Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
  • Page 33 HD151TS207SS DC Electrical Characteristics / USB & VCH 48MHz Clock (CK409T Type3A Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Output Voltage Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
  • Page 34 HD151TS207SS DC Electrical Characteristics / DOT Clock (CK409T Type3B Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Output Voltage Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
  • Page 35 HD151TS207SS DC Electrical Characteristics / REF Clock (CK409T Type5 Buffer) Ta = 0°C to 70°C, VDD = 3.3 V Item Symbol Output Voltage Output Current Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
  • Page 36 HD151TS207SS Clock Out Fig.1 Cycle to Cycle Jitter (3.3V Single Ended Clock Output) Clock Outx Clock Outy Fig.2 Output Clock Skew (3.3V Single Ended Clock Output) = 33.2 Ω TS207 = 33.2 Ω CPU# I(ref) 475 Ω 49.9 Ω Fig.3 Load Circuit for CPU/CPU# Rev.1.00, Apr.25.2003, page 36 of 38...
  • Page 37 HD151TS207SS Package Dimensions 18.40 0.25 0.10(0.004) Rev.1.00, Apr.25.2003, page 37 of 38 10.35 0.635 Unit : mm 0˚– 8˚ 0.76...
  • Page 38 Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.