Table of Contents
Advertisement
CMNCR.DMAIW
Setting
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
n (n>=6)
BSC Register Setting*
CS3WCR.WTRP
Setting
3
3
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
Section 12 Bus State Controller (BSC)
2
CS3WCR.TRWL
Setting
2
3
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Rev. 4.00 Sep. 14, 2005 Page 397 of 982
Minimum Number of
Idle Cycles
5
6
3
3
3
3
3
3
4
3
3
4
5
3
4
5
6
4
4
4
4
4
4
4
4
4
4
4
5
4
4
5
6
n
REJ09B0023-0400
Advertisement
Table of Contents
