Figure 12.19 Burst Read Wait Specification Timing (Cas Latency 2, Wtrcd1 And Wtrcd0 = 1 Cycle, Auto Pre-Charge) - Renesas HD6417641 Hardware Manual

Tr
CKIO
A25 to A0
1
A12/A11*
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.19 Burst Read Wait Specification Timing
(CAS Latency 2, WTRCD1 and WTRCD0 = 1 Cycle, Auto Pre-Charge)
Tw
Trw Tc1 Tc2
Section 12 Bus State Controller (BSC)
Td1 Td2 Td3
Tc3 Tc4
Rev. 4.00 Sep. 14, 2005 Page 353 of 982
Td4
Tde (Tap)
REJ09B0023-0400