Table 13.7 Selecting On-Chip Peripheral Module Request Modes With The Rs3 To Rs0 Bits - Renesas HD6417641 Hardware Manual

Section 13 Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request: In this mode, the transfer is performed in response to the
DMA transfer request signal of an on-chip peripheral module. Signals that request DMA transfer
include A/D conversion-completed transfer requests from A/D converter 0, compare-match
transfer requests from the CMT0 timer, transmit-data empty transfer requests and receive-data full
transfer requests from the SCIF0 to SCIF2 that are set by DMARS0 and 1, compare-match and
input-capture interrupts from the MTU0 to MTU4 timers, transmit-data-empty transfer requests
and receive-data-full transfer requests from the USB module, A/D conversion-completed transfer
requests from A/D converter 1, and compare-match transfer requests from the CMT1 timer.
When the transfer request is a transmit-data-empty transfer request, set the transfer destination as
the corresponding SCIF transmit-data register. Likewise, when the transfer request is a receive-
data full transfer request, set the transfer destination as the corresponding SCIF receive-data
register. Requests from the USB are handled in an analogous way. If a transfer is requested from
the A/D converter 0 and A/D converter 1, the transfer source must be the A/D data register
(ADDR). Any address can be specified for data source and destination, when transfer request is
generated by CMT0, CMT1, and MTU0 to MTU4.

Table 13.7 Selecting On-Chip Peripheral Module Request Modes with the RS3 to RS0 Bits

CHCR DMARS
RS[3:0] MID RID
1110 Any Any A/D converter 0 ADI (A/D conversion
1111 Any Any CMT0
1000 100010 00
01
100100 00
01
010000 00
01
Rev. 4.00 Sep. 14, 2005 Page 428 of 982
REJ09B0023-0400
DMA Transfer
Request DMA Transfer
Source Request Signal
end interrupt)
Compare-match transfer
request
SCIF0 TXI (transmit data FIFO
transmitter empty interrupt)
SCIF0 receiver RXI (receive data FIFO
full interrupt)
SCIF1 TXI (transmit data FIFO
transmitter empty interrupt)
SCIF1 receiver RXI (receive data FIFO
full interrupt)
SCIF2 TXI (transmit data FIFO
transmitter empty interrupt)
SCIF2 receiver RXI (receive data FIFO
full interrupt)
Source Destination Bus Mode
ADDR Any
Any Any
Any SCFTDR0
SCFRDR0 Any
Any SCFTDR1
SCFRDR1 Any
Any SCFTDR2
SCFRDR2 Any
Cycle steal
Burst/
cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal
Cycle steal