Renesas HD6417641 Hardware Manual page 756

Section 19 Serial Communication Interface with FIFO (SCIF)
Bit Bit Name
0 DR
Note: The only value that can be written is 0 to clear the flag.
*
Rev. 4.00 Sep. 14, 2005 Page 706 of 982
REJ09B0023-0400
Initial
value R/W Description
0 R/(W)* Receive Data Ready
Indicates that the quantity of data in the receive FIFO
data register (SCFRDR) is less than the specified
receive trigger number, and that the next data has not
yet been received after the elapse of 15 ETU from the
last stop bit in asynchronous mode. In clock
synchronous mode, this bit is not set to 1.
0: Receiving is in progress, or no receive data
[Clearing conditions]
•
•
•
1: Next receive data has not been received
[Setting condition]
•
Note: * This is equivalent to 1.5 frames with the 8-bit,
remains in SCFRDR after receiving ended normally
DR is cleared to 0 when the chip undergoes a
power-on reset
DR is cleared to 0 when all receive data are read
after 1 is read from DR and then 0 is written
DR is cleared to 0 when all receive data are read
by DMAC
DR is set to 1 when SCFRDR contains less data
than the specified receive trigger number, and the
next data has not yet been received after the
elapse of 15 ETU from the last stop bit.*
1-stop-bit format. (ETU: elementary time unit)