Renesas HD6417641 Hardware Manual page 99

Addressing Instruction
Mode Format
Register @(disp:4, Rn)
indirect with
displacement
Indexed @(R0, Rn)
register indirect
GBR @(disp:8, GBR) Effective address is register GBR contents
indirect with
displacement
Indexed GBR @(R0, GBR)
indirect
Effective Address Calculation Method
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte),
2 (word), or 4 (longword), according to the
operand size.
Rn
+
disp
(zero-extended)
×
1/2/4
Effective address is sum of register Rn and
R0 contents.
Rn
+
R0
with 8-bit displacement disp added.
After disp is zero-extended, it is multiplied by
1 (byte), 2 (word), or 4 (longword), according
to the operand size.
GBR
+
disp
(zero-extended)
×
1/2/4
Effective address is sum of register GBR and
R0 contents.
GBR
+
R0
Calculation Formula
Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn + disp × 4
Rn
+ disp × 1/2/4
Rn + R0
Rn + R0
Byte: GBR + disp
Word: GBR + disp × 2
Longword: GBR + disp × 4
GBR
+ disp × 1/2/4
GBR + R0
GBR + R0
Rev. 4.00 Sep. 14, 2005 Page 49 of 982
Section 2 CPU
REJ09B0023-0400