Figure 3.15 Single Data-Transfer Operation Flow (Word) - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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Section 3 DSP Operation
Note: Data transfer by an LDS or STS instruction is possible since DSR is defined as a system
register.

Figure 3.15 Single Data-Transfer Operation Flow (Word)

Rev. 4.00 Sep. 14, 2005 Page 120 of 982
REJ09B0023-0400
Pointer (R2, R3, R4, R5)
X0
X1
A0
A1
Not affected for store and cleared for load
See description of A0G and A1G.
LAB [31:0]
Any memory areas
LDB [15:0]
Y0
Y1
M0
M1
A0G
–2, 0, +2, +R8
A1G
DSR
Cannot be specified

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