Dma Operation Register (Dmaor) - Renesas HD6417641 Hardware Manual

Section 13 Direct Memory Access Controller (DMAC)
13.3.5

DMA Operation Register (DMAOR)

The DMA operation register (DMAOR) is a 32-bit read/write register that specifies the priority
level of channels at the DMA transfer. This register shows the DMA transfer status. The DMAOR
is initialized to H'00000000 at reset and retains the current value in the standby or module standby
mode.
Bit Bit Name

31, 30
29 CMS1
28 CMS0

27, 26
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Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Cycle Steal Mode Select 1, 0
0 R/W These bits select either normal mode or intermittent
mode in cycle steal mode.
It is necessary that the bus modes of all channels be
set to cycle steal mode to make the intermittent mode
valid.
00: Normal mode
01: Reserved (Setting prohibited)
10: Intermittent mode 16
11: Intermittent mode 64
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Executes one DMA transfer in each of 16 clocks of
an external bus clock.
Executes one DMA transfer in each of 64 clocks of
an external bus clock.