Figure 2.14 Modulo Addressing - Renesas HD6417641 Hardware Manual

MOV.L ModAddr,Rn;
LDC Rn,MOD;
ModAddr: .DATA.W
.DATA.W
ModStart: .DATA
:
ModEnd: .DATA
The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1.
When the X/Y data transfer instruction set in DMX/DMY is executed, the address register
contents before update are compared with ME*
in the address register as the updated value*
specified for the X/Y data transfer instruction, the address pointer will not return to modulo start
address MS even though the address register contents match ME.
Notes: 1. Bits 1 to 15 of the address register are used for comparison. Though ME retains its
previous value for bit 0, 0 must always be written to bit 0.
2. The MS value is stored in bits 1 to 15 of the address register. Though MS retains its
previous value for bit 0, 0 must always be written to bit 0.
The maximum modulo size is 64-kbytes. This is sufficient to access the X and Y data memory. A
block diagram of modulo addressing is shown in figure 2.14.
31 0
R8[Ix]
+2
+0
ALU
Rn=ModEnd, ModStart
ME=ModEnd, MS=ModStart
mEnd;
mStart;
2
. If non-update address register addressing is
Instruction (MOVX/MOVY)
DMX
31 16 15 0
R4[Ax]
R5[Ax]
15
ABx
15 1 15
XAB

Figure 2.14 Modulo Addressing

ModEnd
ModStart
1
. If they match, modulo start address MS is stored
DMY
31 16 15
R6[Ay]
R7[Ay]
CONT
1
MS
CMP
ME ABy
1 15
YAB
Rev. 4.00 Sep. 14, 2005 Page 55 of 982
Section 2 CPU
0
31 0
R9[Iy]
+2
+0
AU
1
REJ09B0023-0400