Renesas HD6417641 Hardware Manual page 344

Section 12 Bus State Controller (BSC)
Bit Bit Name

5 to 2
1 HW1
0 HW0
• CS5BWCR
Bit Bit Name

31 to 22
21 SZSEI
Rev. 4.00 Sep. 14, 2005 Page 294 of 982
REJ09B0023-0400
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Delay Cycles from RD, WEn Negation to Address,
0 R/W
CSn Negation
0 R/W
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W MPX-IO Interface Bus Width Specification
Specifies an address to select the bus width when the
BSZ[1:0] of CS5BBCR are specified as 11. This bit is
valid only when area 5B is specified as MPX-I/O.
0: Selects the bus width by address A14
1: Selects the bus width by address A21
The relationship between the SZSEL bit and bus width
selected by A14 or A21 are summarized below.
SZSEL A14
0
0
1
1
A21 Bus Width
0 Not affected
0 Not affected
Not affected 0
Not affected 1
8 bits
16 bits
8 bits
16 bits