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Section 12 Bus State Controller (BSC)
(2) Transfer from the normal space interface to the external device with DACK
BSC Register Setting*
CSnWCR.WM Setting
1
0
1
0
1
0
1
0
0, 1
Notes:
DMAC is operated by Bφ. The minimum number of idle cycles is not affected by
changing a clock ratio.
1. Minimum number of idle cycles between the upper and lower 16-bit access cycles in the
32-bit access cycle when the bus width is 16 bits, and the minimum number of idle
cycles between continuous access cycles during 16-byte transfer
2. Other than the above cases.
3. For single transfer from the external device with DACK to the normal space interface,
the minimum number of idle cycles is not affected by the IWW, IWRWD, IWRWS,
IWRRD, and IWRRS bits in CSnBCR.
4. For single transfer from the normal space interface to the external device with DACK,
the minimum number of idle cycles is not affected by the DMAIWA and DMAIW bits in
CMNCR.
Rev. 4.00 Sep. 14, 2005 Page 392 of 982
REJ09B0023-0400
4
CSnBCR Idle Setting
0
0
1
1
2
2
4
4
n (n≥6)
When Access Size is Less than Bus Width
Continuous
1
Transfer*
0
1
1
1
2
2
4
4
n
Non-Continuous
2
Transfer*
3
3
3
3
3
3
4
4
n
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