Table 2.15 Single Data Transfer Instruction Formats - Renesas HD6417641 Hardware Manual

Table 2.15 Single Data Transfer Instruction Formats

Type Mnemonic
Single MOVS.W @-As,Ds
data MOVS.W @As,Ds
transfer MOVS.W @As+,Ds
MOVS.W @As+Ix,Ds
MOVS.W Ds,@-As
MOVS.W Ds,@As
MOVS.W Ds,@As+
MOVS.W Ds,@As+Ix
MOVS.L @-As,Ds
MOVS.L @As,Ds
MOVS.L @As+,Ds
MOVS.L @As+Ix,Ds
MOVS.L Ds,@-As
MOVS.L Ds,@As
MOVS.L Ds,@As+
MOVS.L Ds,@As+Ix
Note: * Codes reserved for system use.
Parallel Processing Instructions: Parallel processing instructions are provided for efficient
execution of digital signal processing using the DSP unit. They are 32 bits long and allow four
simultaneous processes, an ALU operation, multiplication, and two data transfers.
Parallel processing instructions are divided into an A field and a B field. The A field defines data
transfer instructions and the B field an ALU operation instruction and multiply instruction. These
instructions can be defined independently, and the processing is executed in parallel,
independently and simultaneously. A-field parallel data transfer instructions are shown in table
2.16, and B-field ALU operation instructions and multiply instructions in table 2.17.
15 14 13 12 11 10 9
1 1 1 1 0
8 7 6 5
1 As Ds 0:(*)
0:R4 1:(*)
1:R5 2:(*)
2:R2 3:(*)
3:R3 4:(*)
5:A1
6:(*)
7:A0
8:X0
9:X1
A:Y0
B:Y1
C:M0
D:A1G
E:M1
F:A0G
Rev. 4.00 Sep. 14, 2005 Page 63 of 982
Section 2 CPU
4 3 2 1 0
0 0 0 0
0 1
1 0
1 1
0 0 0 1
0 1
1 0
1 1
0 0 1 0
0 1
1 0
1 1
0 0 1 1
0 1
1 0
1 1
REJ09B0023-0400