Renesas HD6417641 Hardware Manual page 234

Section 7 Cache
Bit Bit Name

31 to 17
16 LE

15 to 10
9 W3LOAD
8 W3LOCK

7 to 2
1 W2LOAD
0 W2LOCK
Note: The W2LOAD and W3LOAD bits should not be set to 1 at the same time.
Rev. 4.00 Sep. 14, 2005 Page 184 of 982
REJ09B0023-0400
Initial
value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Lock Enable
This bit enables or disables the cache locking function.
0: Cache locking mode is entered when SR.DSP=1
1: Cache locking mode is entered regardless of the
value of SR.DSP
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Way 3 Load
0 R/W Way 3 Lock
When a cache miss occurs by the prefetch instruction
while W3LOAD = 1 and W3LOCK = 1 in cache locking
mode, the data is always loaded into way 3. Under any
other condition, the prefetched data is loaded into the
way to which LRU points.
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
0 R/W Way 2 Load
0 R/W Way 2 Lock
When a cache miss occurs by the prefetch instruction
while W2LOAD = 1 and W2LOCK in cache locking
mode, the data is always loaded into way 2. Under any
other condition, the prefetched data is loaded into the
way to which LRU points.