Figure 13.16 Example Of Dreq Input Detection In Burst Mode Level Detection; Figure 13.17 Example Of Dreq Input Detection In Burst Mode Level Detection - Renesas HD6417641 Hardware Manual

Section 13 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)

Figure 13.16 Example of DREQ Input Detection in Burst Mode Level Detection

Figure 13.17 shows the TEND output timing.
CKIO
Bus cycle
DREQ
DACK
TEND

Figure 13.17 Example of DREQ Input Detection in Burst Mode Level Detection

Rev. 4.00 Sep. 14, 2005 Page 442 of 982
REJ09B0023-0400
CPU CPU
1st acceptance
Non sensitive period
CPU CPU
1st acceptance
Non sensitive period
End of DMA transfer
DMAC CPU
DMAC
2nd acceptance
Acceptance
start
DMAC
DMAC
3rd
2nd acceptance
acceptance
Acceptance Acceptance
start start
DMAC CPU CPU