Port G Data Register - Renesas HD6417641 Hardware Manual

23.7.2 Port G Data Register (PGDR)
PGDR a register that includes six readable/writable and eight readable bits with two reserved bits
that store data for pins PTG13 to PTG0.
PGDR13 to PGDR8 are initialized to H'00 by a power-on reset, but they retain their previous
values by a manual reset, in standby mode, or in sleep mode. PGDR7 to PGDR0 are not initialized
by a power-on or manual reset, in standby mode, or in sleep mode. (The bit always indicates the
status of the pin.)
Bit Bit Name

15, 14
13 PG13DT
12 PG12DT
11 PG11DT
10 PG10DT
9 PG9DT
8 PG8DT
7 PG7DT
6 PG6DT
5 PG5DT
4 PG4DT
3 PG3DT
2 PG2DT
1 PG1DT
0 PG0DT
Note: The initial value depends on the status of the pin at reading.
*
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0 R/W Bits PG13DT to PG8DT correspond to pins PTG13 to
PTG8. When the function is general input port, the
0 R/W
corresponding pin level is read by reading the port.
0 R/W
Tables 23.8 and 23.9 show the function of PGDRs 13
to 8.
0 R/W
0 R/W
0 R/W
0 R/W Bits PG7DT to PG0DT correspond to pins PTG7 to
PTG0. The values written to these bits are ignored and
0 R/W
does not affect pin state. If these bits are read, the
0 R/W
states of the pins are returned directly instead of the
values of these bits. Do not read these bits when the
0 R/W
A/D converter is used. Table 23.10 shows the function
0 R/W
of PGDR.
0 R/W
0 R/W
0 R/W
Section 23 I/O Ports
Rev. 4.00 Sep. 14, 2005 Page 857 of 982
REJ09B0023-0400