Renesas HD6417641 Hardware Manual page 345

Bit Bit Name
20 MPX
BAS

19
18 WW2
17 WW1
16 WW0

15 to 13
Initial
Value R/W Description
0 R/W MPX-IO Interface Address Wait
Specifies the address cycle insertion wait for MPX-IO
interface. This bit setting is valid only when area 5B is
specified as MPX-I/O.
0: Inserts no wait cycle
1: Inserts 1 wait cycle
0 R/W Byte-Selection SRAM Byte Access Selection
This bit setting is valid only when area 5B is specified
as byte-selection SRAM.
Specifies the WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read access cycle
0 R Reserved
This bit is always read as 0. The write value should
always be 0.
0 R/W Number of Write Access Wait Cycles
0 R/W Specify the number of cycles that are necessary for
write access.
0 R/W
000: The same cycles as WR[3:0] setting (number of
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Section 12 Bus State Controller (BSC)
asserts the RD/WR signal during the write access
cycle.
and asserts the RD/WR signal at the write timing.
read access wait cycles)
Rev. 4.00 Sep. 14, 2005 Page 295 of 982
REJ09B0023-0400