Table 2.22 Shift Instructions - Renesas HD6417641 Hardware Manual

Section 2 CPU
Shift Instructions

Table 2.22 Shift Instructions

Instruction Instruction Code
ROTL Rn 0100nnnn00000100
ROTR Rn 0100nnnn00000101
ROTCL Rn 0100nnnn00100100
ROTCR Rn 0100nnnn00100101
SHAD Rm,Rn 0100nnnnmmmm1100
SHAL Rn 0100nnnn00100000
SHAR Rn 0100nnnn00100001
SHLD Rm,Rn 0100nnnnmmmm1101
SHLL Rn 0100nnnn00000000
SHLR Rn 0100nnnn00000001
SHLL2 Rn 0100nnnn00001000
SHLR2 Rn 0100nnnn00001001
SHLL8 Rn 0100nnnn00011000
SHLR8 Rn 0100nnnn00011001
SHLL16 Rn 0100nnnn00101000
SHLR16 Rn 0100nnnn00101001
Rev. 4.00 Sep. 14, 2005 Page 76 of 982
REJ09B0023-0400
Operation
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
Rm ≥ 0: Rn << Rm → Rn
Rm < 0: Rn >> Rm →
[MSB → Rn]
T ← Rn ← 0
MSB → Rn → T
Rm ≥ 0: Rn << Rm → Rn
Rm < 0: Rn >> Rm →
[0 → Rn]
T ← Rn ← 0
0 → Rn → T
Rn << 2 → Rn
Rn >> 2 → Rn
Rn << 8 → Rn
Rn >> 8 → Rn
Rn << 16 → Rn
Rn >> 16 → Rn
Execution
States T Bit
1 MSB
1 LSB
1 MSB
1 LSB
1 —
1 MSB
1 LSB
1 —
1 MSB
1 LSB
1 —
1 —
1 —
1 —
1 —
1 —