Figure 25.26 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Auto Precharge, Cas Latency 2, Wtrcd = 1 Cycle, Wtrp = 0 Cycle) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
CKIO
t
AD1
A25 to A0
t
AD1
1
A12/A11*
t
CSD1
CSn
t
RWD1
RD/WR
t
RASD1
RASU/L
CASU/L
t
DQMD1
DQMxx
D31 to D0
BS
CKE
t
DACD
DACKn*
2
Note:
Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Auto Precharge, CAS Latency 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)
Rev. 4.00 Sep. 14, 2005 Page 938 of 982
REJ09B0023-0400
Tr Trw Tc1 Tc2
t t
AD1 AD1
Row
address
t
AD1
Read command
t
RASD1
t
CASD1
t
BSD
(High)
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Td1 Td2
Tc3 Tc4
t t
AD1 AD1
Column
(1 to 4)
address
t t
AD1 AD1
ReadA
command
t
CASD1
t t
RDS2 RDH2
t
BSD
Td3 Td4
Tde
t
AD1
t
CSD1
t
RWD1
t
DQMD1
t t
RDS2 RDH2
t
DACD