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Section 18 Multi-Function Timer Pulse Unit (MTU)
Input/output pins
Channel 3:
TIOC3A
TIOC3B
TIOC3C
TIOC3D
Channel 4:
TIOC4A
TIOC4B
TIOC4C
TIOC4D
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
Internal clock
External clock
TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0:
TIOC0A
TIOC0B
TIOC0C
TIOC0D
Channel 1:
TIOC1A
TIOC1B
Channel 2:
TIOC2A
TIOC2B
[Legend]
TSTR:
Timer start register
TSYR:
Timer synchro register
TCR:
Timer control register
TMDR:
Timer mode register
TIOR (H, L):
Timer I/O control registers (H, L)
Rev. 4.00 Sep. 14, 2005 Page 520 of 982
REJ09B0023-0400
TIER:
TSR:
TCNT:
TGR (A, B, C, D):
Figure 18.1 Block Diagram of MTU
Interrupt request signals
Channel 3:
Channel 4:
DMA transfer request signal
Channel 0: TGI3A
Channel 1: TGI4A
Internal data bus
A/D converter conversion
start signal
Interrupt request signals
Channel 0:
Channel 1:
Channel 2:
DMA transfer request signal
Timer interrupt enable register
Timer status register
Timer counter
Timer general registers (A, B, C, D)
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
TGI4A
TGI4B
TCI4C
TCI4D
TGI4V
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
Channel 0: TGI0A
Channel 1: TGI1A
Channel 2: TGI2A
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