Figure 12.39 Byte-Selection Sram Wait Timing (Bas = 1) (Sw[1:0] = 01, Wr[3:0] = 0001, Hw[1:0] = 01) - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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Section 12 Bus State Controller (BSC)
CKIO
A25 to A0
CSn
WEn
RD/WR
RD
Read
D31 to D0
RD/WR
RD
Write
D31 to D0
BS
DACKn*
Figure 12.39 Byte-Selection SRAM Wait Timing (BAS = 1)
Rev. 4.00 Sep. 14, 2005 Page 380 of 982
REJ09B0023-0400
Th
Note: * The waveform for DACKn is when active low is specified.
(SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)
T1
Tw
High
T2
Th

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