Figure 20.13 Forcible Stall By Application - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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(1) Transition from normal operation to stall
(1-1)
USB
(1-2)
Transaction request
(1-3)
STALL handshake
(2) When Clear Feature is sent after USBEPSTL is cleared
(2-1)
Transaction request
(2-2)
STALL handshake
(2-3)
Clear Feature command
(3) When Clear Feature is sent before USBEPSTL is cleared to 0
(3-1)
Clear Feature command

Figure 20.13 Forcible Stall by Application

Internal status bit
0
Reference
Internal status bit
0
Stall
Internal status bit
0 → 1
To (2-1) or (3-1)
Internal status bit
1
Internal status bit
1
Internal status bit
1 → 0
Normal status restored
Internal status bit
1 → 0
To (1-2)
Section 20 USB Function Module
1. 1 written to
USBEPSTL
USBEPSTL by
0 → 1
application
1. IN/OUT token
USBEPSTL
received from host
1
2. USBEPSTL
referenced
1. 1 set in USBEPSTL
2. Internal status bit
USBEPSTL
set to 1
1
3. Transmission of
STALL handshake
1. USBEPSTL cleared
to 0 by application
2. IN/OUT token
USBEPSTL
received from host
1 → 0
3. Internal status bit
already set to 1
4. USBEPSTL not
referenced
5. Internal status bit
not changed
1. Transmission of
USBEPSTL
STALL handshake
0
1. Internal status bit
USBEPSTL
cleared to 0
0
1. Internal status bit
cleared to 0
USBEPSTL
2. USBEPSTL not
1
changed
Rev. 4.00 Sep. 14, 2005 Page 781 of 982
REJ09B0023-0400

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