Table 2.3 Source Register In Dsp Operations - Renesas HD6417641 Hardware Manual

Section 2 CPU
Table 2.3 Source Register in DSP Operations
Registers
A0, A1 DSP
Data
transfer
A0G, A1G Data
transfer
X0, X1 DSP
Y0, Y1
M0, M1
Data
transfer
Note: * The data is sign-extended and input to the ALU.
Rev. 4.00 Sep. 14, 2005 Page 38 of 982
REJ09B0023-0400
Instructions
Fixed-point, PDMSB,
PSHA
Integer
Logical, PSHL, PMULS
MOVX/Y.W, MOVS.W
MOVS.L
MOVS.W
MOVS.L
Fixed-point, PDMSB,
PSHA
Integer
Logical, PSHL, PMULS
MOVS.W
MOVS.L
Guard Bits Register Bits
39 32 31
40-bit data
24-bit data
16-bit data
16-bit data
32-bit data
Data
Data
Sign* 32-bit data
Sign* 16-bit data
16-bit data
16-bit data
32-bit data
16 15 0