Table 2.2 Destination Register In Dsp Instructions - Renesas HD6417641 Hardware Manual

Table 2.2 Destination Register in DSP Instructions
Registers
A0, A1 DSP
Data
transfer
A0G, A1G Data
transfer
X0, X1 DSP
Y0, Y1
M0, M1
Data
transfer
Instructions
Fixed-point, PSHA,
PMULS
Integer, PDMSB
Logical, PSHL
MOVS.W
MOVS.L
MOVS.W
MOVS.L
Fixed-point, PSHA,
PMULS
Integer, logical,
PDMSB, PSHL
MOVX/Y.W, MOVS.W
MOVS.L
Guard Bits Register Bits
39 32 31
Sign-extended 40-bit result
Sign-extended 24-bit result
Cleared 16-bit result
Sign-extended 16-bit data
Sign-extended 32-bit data
Data No update
Data No update
32-bit result
16-bit result
16-bit result
32-bit data
Rev. 4.00 Sep. 14, 2005 Page 37 of 982
Section 2 CPU
16 15 0
Cleared
Cleared
Cleared
Cleared
Cleared
REJ09B0023-0400