Renesas HD6417641 Hardware Manual page 254

Section 9 Exception Handling
Table 9.1 Exception Event Vectors
Exception Current
Type Instruction
Reset Aborted
General Re-executed
exception
events
Completed
General Completed
exception
events
General Completed
interrupt
requests
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest.
A reset has the highest priority. An interrupt is accepted only when general exceptions
are not requested.
2. For details on priorities in multiple interrupt sources, refer to section 10, Interrupt
Controller (INTC).
3. If an interrupt is accepted, the exception event register (EXPEVT) is not changed. The
interrupt source code is specified in interrupt source register 2 (INTEVT2). For details,
refer to section 10, Interrupt Controller (INTC).
4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code
and vector offset are specified.
Rev. 4.00 Sep. 14, 2005 Page 204 of 982
REJ09B0023-0400
Exception Event
Power-on reset
Manual reset
H-UDI reset
User break
(before instruction execution)
CPU address error
4
(instruction access) *
Illegal general instruction exception
Illegal slot instruction exception
CPU address error (data access)*
Unconditional trap
(TRAPA instruction)
User breakpoint
(After instruction execution, address)
User breakpoint
(Data break, I-BUS break)
DMA address error
Interrupt requests
Exception
1
Priority* Order
1 1
1 2
1 1
2 0
2 1
2 2
2 2
4
2 3
2 4
2 5
2 5
2 6
2
3 —*
Process Vector Vector
at BL=1 Code Offset

Reset H'A00
Reset H'020 —
Reset H'000 —
Ignored H'1E0 H'00000100
Reset H'0E0 H'00000100
Reset H'180 H'00000100
Reset H'1A0 H'00000100
Reset H'0E0/ H'00000100
H'100
Reset H'160 H'00000100
Ignored H'1E0 H'00000100
Ignored H'1E0 H'00000100
Retained H'5C0 H'00000100
3
Retained —* H'00000600