Renesas HD6417641 Hardware Manual page 354

Section 12 Bus State Controller (BSC)
Bit Bit Name
17 BW1
16 BW0

15 to 13
12 SW1
11 SW0
Rev. 4.00 Sep. 14, 2005 Page 304 of 982
REJ09B0023-0400
Initial
Value R/W Description
0 R/W Number of Burst Wait Cycles
0 R/W Specify the number of wait cycles to be inserted
between the second or later access cycles in burst
access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CSn Assertion
0 R/W
to RD, WE Assertion
0 R/W
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles