Bus Cycle Of Byte-Selection Sram; Figure 25.20 Byte-Selection Sram Bus Cycle (Sw = 1 Cycle, Hw = 1 Cycle, One Asynchronous External Wait Cycle, Bas = 0 (Write Cycle Ub/Lb Control)) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
25.3.5

Bus Cycle of Byte-Selection SRAM

CKIO
A25 to A0
CSn
WEn
RD/WR
RD
Read
D31 to D0
RD/WR
Write
D31 to D0
BS
DACKn,
TENDn*
WAIT
Note: * Waveform for DACKn and TENDn when active low is selected.
Figure 25.20 Byte-Selection SRAM Bus Cycle (SW = 1 Cycle, HW = 1 Cycle, One
Asynchronous External Wait Cycle, BAS = 0 (Write Cycle UB/LB Control))
Rev. 4.00 Sep. 14, 2005 Page 932 of 982
REJ09B0023-0400
Th T1
t
AD1
t
CSD1
t
WED1
t
RWD1
t
RSD
t
RWD1
t
WDD1
t t
BSD BSD
t
DACD
t
WTH1
t
WTS1
Twx T2
t
WED1
t
RSD
t
RDH1
t
RDS1
t
WTH1
t
WTS1
Tf
t
AD1
t
CSD1
t
RWD1
t
RWD1
t
WDH1
t
DACD