Reset; Table 6.1 States Of Power-Down Modes - Renesas HD6417641 Hardware Manual

Section 6 Power-Down Modes
Table 6.1 States of Power-Down Modes
Mode Transition Conditions
Sleep mode Execute SLEEP
instruction with STBY bit
cleared to 0 in STBCR
Standby mode Execute SLEEP
instruction with STBY bit
set to 1 in STBCR
Module standby Set the MSTP bits in
function STBCR, STBCR2,
STBCR3, and STBCR4
to 1 (with the exception
of the MSTP bits for the
USB module; clear these
bits).
Note: The pin state is retained or set to high impedance. For details, see Appendix A, Pin
*
States.
6.1.2

Reset

A reset is used at power-on or to re-execute from the initial state. This LSI supports two types of
reset: power-on reset and manual reset. In power-on reset, any processing to be currently executed
is terminated and any events not executed are canceled to execute reset processing immediately. In
manual reset, processing required to maintain external memory contents is continued. The
following shows the conditions in which power-on reset or manual reset occurs.
• Power-on reset
1. A low level signal is input to the RESETP pin.
2. The WDT counter overflows if WDT starts counting while the WT/IT and RSTS bits of the
WTCSR are set to 1 and cleared to 0, respectively.
3. An H-UDI reset occurs. (For details on H-UDI reset, refer to section 15, User Debugging
Interface (H-UDI).)
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State*
CPU On-Chip
CPG CPU Register Memory
Runs Halts Held Halts
(The contents
are retained.)
Halts Halts Held Halts
(The contents
are retained.)
Runs Runs Held The specified
module stops
(the contents are
retained).
On-Chip
Peripheral External
Modules Memory
The UBC stops. Refreshed
Other modules automati-cally
continue to run.
Halt Self-refreshed 1.
Specified Refreshed
module halts automati-cally
Canceling
Procedure
1. Interrupt
2. Reset
Interrupt
2. Reset
1. Clear MSTP bit to
0. (with the
exception of the
MSTP bits for the
USB module; set
these bits).
2. Power-on reset