Figure 25.31 Synchronous Dram Burst Read Bus Cycle (Four Read Cycles) (Bank Active Mode: Act + Read Commands, Cas Latency 2, Wtrcd = 0 Cycle) - Renesas HD6417641 Hardware Manual

CKIO
t
A25 to A0
t
1
A12/A11*
t
CSn
t
RD/WR
t
RASU/L
CASU/L
t
DQMxx
D31 to D0
BS
CKE
DACKn*
2
Note:
Figure 25.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: ACT + READ Commands, CAS Latency 2, WTRCD = 0 Cycle)
Tr Tc1 Tc2
t t
AD1 AD1 AD1
Row
Column
address
address
t
AD1 AD1
CSD1
RWD1
t
RASD1 RASD1
t
CASD1
DQMD1
t
BSD
t
DACD
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Section 25 Electrical Characteristics
Td1 Td2 Td3
Tc3 Tc4
t t
AD1 AD1
Read command
t
CASD1
t t
RDS2 RDH2
t
BSD
(High)
Rev. 4.00 Sep. 14, 2005 Page 943 of 982
Td4
Tde
t
AD1
t
AD1
t
CSD1
t
RWD1
t
DQMD1
t t
RDS2 RDH2
t
DACD
REJ09B0023-0400