Figure 25.28 Synchronous Dram Single Write Bus Cycle (Auto Precharge, Wtrcd = 2 Cycles, Trwl = 1 Cycle) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
CKIO
A25 to A0
A12/A11*
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
CKE
DACKn*
Note: 1. An address pin to be connected to pin A10 of SDRAM.
Figure 25.28 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)
Rev. 4.00 Sep. 14, 2005 Page 940 of 982
REJ09B0023-0400
Tr
t
AD1
Row address
t
AD1
1
t
CSD1
t
RWD1
t t
RASD1 RASD1
t
DQMD1
BS
t
DACD
2
2. Waveform for DACKn when active low is selected.
Trw Trw Tc1
t
AD1
Column
address
t
AD1
WriteA
command
t
RWD1
t
CASD1
t
WDD2
t
BSD
(High)
Trwl
t
AD1
t
AD1
t
CSD1
t
RWD1
t
CASD1
t
DQMD1
t
WDH2
t
BSD
t
DACD