Renesas HD6417641 Hardware Manual page 110

Section 2 CPU
Instruction Format
d type
15
xxxx xxxx dddd
d12 type
15
xxxx dddd dddd
nd8 type
15
xxxx nnnn
dddd
i type
15
xxxx xxxx
i i i i
ni type
15
xxxx nnnn i i i i
Rev. 4.00 Sep. 14, 2005 Page 60 of 982
REJ09B0023-0400
Source
Operand
dddddddd: GBR
indirect with
0
displacement
dddd
R0 (register direct) dddddddd: GBR
dddddddd:
PC-relative with
displacement
dddddddd:
PC-relative
dddddddddddd:
PC-relative
0
dddd
dddddddd: PC-
relative with
0
displacement
dddd
iiiiiiii:
immediate
0
i i i i
iiiiiiii:
immediate
iiiiiiii:
immediate
iiiiiiii:
immediate
0
i i i i
Destination
Operand Sample Instruction
R0 (register direct) MOV.L @(disp,GBR),R0
MOV.L
indirect with @R0,@(disp,GBR)
displacement
R0 (register direct) MOVA @(disp,PC),R0

BF

BRA
nnnn: register MOV.L @(disp,PC),Rn
direct
Indexed GBR AND.B
indirect #imm,@(R0,GBR)
R0 (register direct) AND

TRAPA #imm
nnnn: register ADD
direct
label
label
(label=disp+PC)
#imm,R0
#imm,Rn