Renesas HD6417641 Hardware Manual page 347

Bit Bit Name

5 to 2
1 HW1
0 HW0
• CS6AWCR
Bit Bit Name

31 to 13
12 SW1
11 SW0
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Delay Cycles from RD, WEn Negation to Address,
0 R/W
CSn Negation
0 R/W
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CSn Assertion
0 R/W
to RD, WE Assertion
0 R/W
Specify the number of delay cycles from address and
CSn assertion to RD and WE assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 297 of 982
REJ09B0023-0400