Figure 12.28 Single Write Timing (Bank Active, Different Row Addresses In The Same Bank) - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
A25 to A0
A12/A11*
RASL, RASU
CASL, CASU
D31 to D0
DACKn*
(Bank Active, Different Row Addresses in the Same Bank)
Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Auto-
refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in
SDCR. A continuous refreshing can be performed by setting the RRC2 to RRC0 bits in RTCSR. If
synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power
consumption for data retention is low, can be activated by setting both the RMODE bit and the
RFSH bit to 1.
Rev. 4.00 Sep. 14, 2005 Page 364 of 982
REJ09B0023-0400
Tp Tpw
CKIO
1
CSn
RD/WR
DQMxx
BS
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 12.28 Single Write Timing
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