Figure 25.38 Synchronous Dram Self-Refreshing Timing (Wtrp = 1 Cycle) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
CKIO
A25 to A0
1
A12/A11*
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
BS
CKE
DACKn*
2
Note:
Figure 25.38 Synchronous DRAM Self-Refreshing Timing
Rev. 4.00 Sep. 14, 2005 Page 950 of 982
REJ09B0023-0400
Tp Tpw Trr
t
AD1
t
AD1
t t t
CSD1 CSD1 CSD1
t t
RWD1 RWD1
t t t
RASD1 RASD1 RASD1
t
CASD1
t
CKED1
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
3. Pins D31 to D16 with weak keeper are retained as weak keepers.
(WTRP = 1 Cycle)
Trc Trc
t
AD1
t
AD1
t
CSD1
t
RASD1
t
CASD1
3
(Hi-Z)*
t
CKED1
Trc Trc
t
RWD1