Table 18.19 Tiorl_0 (Channel 0) - Renesas HD6417641 Hardware Manual

Table 18.19 TIORL_0 (Channel 0)

Bit 3 Bit 2 Bit 1
IOC3 IOC2 IOC1
0 0 0
1
1 0
1
1 0 0
1
1 X
[Legend]
X: Don't care
Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset
and entering standby mode.
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Bit 0 TGRC_0
IOC0 Function
0 Output
compare
1
2
register*
0
1
0
1
0
1
0 Input capture
2
register*
1
X
X
Section 18 Multi-Function Timer Pulse Unit (MTU)
Description
TIOC0C Pin Function
1
Output hold*
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
1
Output hold*
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Rev. 4.00 Sep. 14, 2005 Page 541 of 982
REJ09B0023-0400