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Section 13 Direct Memory Access Controller (DMAC)
Bit
Bit Name
13
SM1
12
SM0
11
RS3
10
RS2
9
RS1
8
RS0
Rev. 4.00 Sep. 14, 2005 Page 412 of 982
REJ09B0023-0400
Initial
Value
R/W
Descriptions
0
R/W
Source Address Mode
0
R/W
SM1 and SM0 select whether the DMA source address
is incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with
DACK.)
00: Fixed source address (Setting prohibited in 16-byte
01: Source address is incremented (+1 in 8-bit transfer,
10: Source address is decremented (–1 in 8-bit
11: Reserved (Setting prohibited)
0
R/W
Resource Select
0
R/W
RS3 to RS0 specify which transfer requests will be
sent to the DMAC. The changing of transfer request
0
R/W
source should be done in the state that DMA enable bit
0
R/W
(DE) is set to 0.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note: External request specification is valid only in
transfer)
+2 in 16-bit transfer, +4 in 32-bit transfer, +16 in
16-byte transfer)
transfer, –2 in 16-bit transfer, –4 in 32-bit transfer;
illegal setting in 16-byte transfer)
0
0
0
External request, dual address mode
0
0
1
Reserved (Setting prohibited)
0
1
0
External request/Single address mode
External address space → external device with DACK
0
1
1
External request/Single address mode
External device with DACK → external address space
1
0
0
Auto request
1
0
1
Reserved (Setting prohibited)
1
1
0
Reserved (Setting prohibited)
1
1
1
Reserved (Setting prohibited)
0
0
0
DMA expansion request module selection specification
0
0
1
Reserved (Setting prohibited)
0
1
0
Reserved (Setting prohibited)
0
1
1
Reserved (Setting prohibited)
1
0
0
Reserved (Setting prohibited)
1
0
1
Reserved (Setting prohibited)
1
1
0
A/D converter 0
1
1
1
CMT0
CHCR_0 and CHCR_1. None of the request
sources can be selected in channels CHCR_2
and CHCR_3.
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