Figure 12.45 Burst Mpx Space Access Timing (Burst Read, No Wait, Or Software Wait 1, Cs6Bwcr.mpxmd = 0) - Renesas HD6417641 Hardware Manual

32-bit risc microcomputer superh risc engine family / sh7641 series
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Section 12 Bus State Controller (BSC)
Tm1
Tmd1w
Tmd1
Tmd2
Tmd3
Tmd4
CKIO
FRAME
A
D0
D1
D2
D3
D31 to D0
A25 to A0
CS6B
RD/WR
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 12.45 Burst MPX Space Access Timing
(Burst Read, No Wait, or Software Wait 1, CS6BWCR.MPXMD = 0)
Rev. 4.00 Sep. 14, 2005 Page 385 of 982
REJ09B0023-0400

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