Renesas HD6417641 Hardware Manual page 742

32-bit risc microcomputer superh risc engine family / sh7641 series
Table of Contents

Advertisement

Section 19 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
6
CHR
5
PE
Rev. 4.00 Sep. 14, 2005 Page 692 of 982
REJ09B0023-0400
Initial
value
R/W
Description
0
R/W
Character Length
Selects 7-bit or 8-bit data in asynchronous mode. In the
synchronous mode, the data length is always eight bits,
regardless of the CHR setting.
0: 8-bit data
1: 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of
0
R/W
Parity Enable
Selects whether to add a parity bit to transmit data and
to check the parity of receive data, in asynchronous
mode. In synchronous mode, a parity bit is neither
added nor checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity bit
the transmit FIFO data register is not
transmitted.
is added to transmit data, depending on the
parity mode (O/E) setting. Receive data parity
is checked according to the even/odd (O/E)
mode setting.

Advertisement

Table of Contents
loading

This manual is also suitable for:

Sh7641

Table of Contents