Register Description; Port E Data Register (Pedr) - Renesas HD6417641 Hardware Manual

Section 23 I/O Ports
23.5.1

Register Description

Port E has the following register.

• Port E data register (PEDR)

23.5.2 Port E Data Register (PEDR)
PEDR is a 16-bit readable/writable register that stores data for pins PTE15 to PTE0. The PEDR is
initialized to H'0000 by a power-on reset, but it retains its previous value by a manual reset, in
standby mode, or in sleep mode.
Bit Bit Name
15 PE15DT
14 PE14DT
13 PE13DT
12 PE12DT
11 PE11DT
10 PE10DT
9 PE9DT
8 PE8DT
7 PE7DT
6 PE6DT
5 PE5DT
4 PE4DT
3 PE3DT
2 PE2DT
1 PE1DT
0 PE0DT
Rev. 4.00 Sep. 14, 2005 Page 852 of 982
REJ09B0023-0400
Initial
Value R/W Description
0 R/W Bits PE15DT to PE0DT correspond to pins PTE15 to
PTE0. When the pin function is general output port, the
0 R/W
value of the corresponding PEDR bit in PEDR is
0 R/W
returned directly by reading the port. When the function
is general input port, the corresponding pin level is read
0 R/W
by reading the port. Table 23.5 shows the function of
0 R/W
PEDR.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W