Section 12 Bus State Controller (BSC)
CKIO
A25 to A0
A12/A11*
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
DACKn*
Figure 12.21 Basic Timing for Burst Write (Auto Pre-Charge)
Rev. 4.00 Sep. 14, 2005 Page 356 of 982
REJ09B0023-0400
Tr
Tc1
1
BS
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tc2
Tc3
Tc4
Trwl
Tap