Figure 25.29 Synchronous Dram Burst Write Bus Cycle (Four Write Cycles) (Auto Precharge, Wtrcd = 0 Cycle, Trwl = 1 Cycle) - Renesas HD6417641 Hardware Manual

Tr
CKIO
t
AD1
A25 to A0 address
t
AD1
1
A12/A11*
t
CSD1
CSn
t
RWD1
RD/WR
t
RASD1
RASU/L
CASU/L
t
DQMD1
DQMxx
D31 to D0
BS
CKE
t
DACD
DACKn*
2
Note: 1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for DACKn when active low is selected.
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle
(Four Write Cycles) (Auto Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle)
Tc1 Tc2
t t
AD1 AD1
Row
Column
address
t
AD1
WRIT command
t
RWD1
t
RASD1
t
CASD1
t t
WDD2 WDH2
t
BSD
(High)
Section 25 Electrical Characteristics
Tc3 Tc4
t t t
AD1 AD1 AD1
t t
AD1
WriteA
command
t
CSD1
t
RWD1
t
CASD1
t
DQMD1
t t
WDD2 WDH2
t
BSD
t
DACD
Rev. 4.00 Sep. 14, 2005 Page 941 of 982
Trwl
AD1
REJ09B0023-0400