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Section 3 DSP Operation
A: Acceptable for any interrupts
B and C: Acceptable for some interrupts
_
RC > 1 :
1. 1 repeated step
instr – 1
instr0
Start(End):
instr1
instr2
4. 4 repeated steps
instr – 1
instr0
Start:
instr1
instr2
instr3
End:
instr4
instr4
RC = 0 :
Acceptable for any interrupts
Figure 3.18 Restriction of Interrupt Acceptance in Repeat Loop
Note 1: Actual Implementation
Repeat start and repeat end registers, RS and RE, specify the repeat start instruction and repeat end
instruction. The actual addresses that are kept in these registers depend on the number of
instructions in the repeat loop. The rule is as follows:
Repeat_Start:
An address of the instruction at the repeat top
Repeat_Start0:
An address of the instruction before one instruction at the repeat top
Repeat_End3:
An address of the instruction before three instructions at the repeat bottom
Table 3.17 RS and RE Setting Rule
1
RS
Repeat_start0 + 8
RE
Repeat_start0 + 4
Rev. 4.00 Sep. 14, 2005 Page 128 of 982
REJ09B0023-0400
2. 2 repeated steps
; A
; B
; C
Start:
; A
End:
5. 5 or more repeated steps
; A
; A
; B
Start:
; C
; C
; C
; A
End:
Number of Instructions in Repeat Loop
2
Repeat_start0 + 6
Repeat_start0 + 4
3. 3 repeated steps
instr – 1
; A
instr0
; B
instr1
; C
Start:
instr2
; C
instr3
; A
End:
instr – 1
; A
instr0
; A
instr1
; A
:
:
instr n – 3
; B
instr n – 2
; C
instr n – 1
; C
instr n
; C
instr n + 1
; A
3
Repeat_start0 + 4
Repeat_start0 + 4
instr – 1
; A
instr0
; B
instr1
; C
instr2
; C
instr3
; C
instr4
; A
≥4
Repeat_start
Repeat_End3 + 4
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