Renesas HD6417641 Hardware Manual page 765

Bit Bit Name
7 RTRG1
6 RTRG0
5 TTRG1
4 TTRG0
3 MCE
Section 19 Serial Communication Interface with FIFO (SCIF)
Initial
value R/W Description
0 R/W Receive FIFO Data Trigger
0 R/W Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register
(SCFSR). The RDF flag is set when the quantity of
receive data stored in the receive FIFO register
(SCFRDR) is increased more than the set trigger
number shown below.
•
0 R/W Transmit FIFO Data Trigger 1, 0
0 R/W Set the quantity of remaining transmit data which sets
the transmit FIFO data register empty (TDFE) flag in the
serial status register (SCFSR). The TDFE flag is set
when the quantity of transmit data in the transmit FIFO
data register (SCFTDR) becomes less than the set
trigger number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of
0 R/W Modem Control Enable
Enables modem control signals CTS and RTS.
In synchronous mode, MCE bit should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the input
Asynchronous mode
00: 1
01: 4
10: 8
11: 14
empty bytes in SCFTDR when the TDFE flag is
set to 1.
value, and RTS is also fixed at 0.
Rev. 4.00 Sep. 14, 2005 Page 715 of 982
•
Synchronous mode
00: 1
01: 2
10: 8
11: 14
REJ09B0023-0400