Single Write: A write access ends in one cycle when data is written in non-cacheable region and
the data bus width is larger than or equal to access size.
Figure 12.22 shows the single write basic timing.
A25 to A0
A12/A11*
RASL, RASU
CASL, CASU
D31 to D0
DACKn*
Figure 12.22 Single Write Basic Timing (Auto-Precharge)
Tr
Tc1
CKIO
1
CSn
RD/WR
DQMxx
BS
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Section 12 Bus State Controller (BSC)
Trwl
Tap
Rev. 4.00 Sep. 14, 2005 Page 357 of 982
REJ09B0023-0400