Renesas HD6417641 Hardware Manual page 356

Section 12 Bus State Controller (BSC)
Bit Bit Name
1 HW1
0 HW0
SDRAM*:
• CS2WCR
Bit Bit Name

31 to 11

10

9
8 A2CL1
7 A2CL0

6 to 0
Rev. 4.00 Sep. 14, 2005 Page 306 of 982
REJ09B0023-0400
Initial
Value R/W Description
Delay Cycles from RD, WEn Negation to Address, CSn
0 R/W
Negation
0 R/W
Specify the number of delay cycles from RD and WEn
negation to address and CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1 R Reserved
This bit is always read as 1. The write value should
always be 1.
0 R Reserved
This bit is always read as 0. The write value should
always be 0.
1 R/W CAS Latency for Area 2
0 R/W Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.