Figure 12.34 Emrs Command Issue Timing; Table 12.16 Output Addresses When Emrs Command Is Issued - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)

Table 12.16 Output Addresses when EMRS Command Is Issued

Command to be
Issued
CS2 MRS
CS3 MRS
CS2 MRS + EMRS
(with refresh)
CS3 MRS + EMRS
(with refresh)
CS2 MRS + EMRS
(without refresh)
CS3 MRS + EMRS
(without refresh)
Tp
PALL
CKIO
A25 to A0
1
BA1*
2
BA0*
3
A12/A11*
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*
4
Notes: 1. Address pin to be connected to pin BA1 of SDRAM.
2. Address pin to be connected to pin BA0 of SDRAM.
3. Address pin to be connected to pin A10 of SDRAM.
4. The waveform for DACKn is when active low is specified.
Rev. 4.00 Sep. 14, 2005 Page 374 of 982
REJ09B0023-0400
Access
Address Access Data
H'A4FD4XX0 H'********
H'A4FD5XX0 H'********
H'A4FD4XX0 H'0YYYYYYY 32 bits
H'A4FD5XX0 H'0YYYYYYY 32 bits
H'A4FD4XX0 H'1YYYYYYY 32 bits
H'A4FD5XX0 H'1YYYYYYY 32 bits
Tpw Trr Trc
REF

Figure 12.34 EMRS Command Issue Timing

Write MRS
Access Command
Size Issue Address
16 bits H'0000XX0
16 bits H'0000XX0
H'0000XX0
H'0000XX0
H'0000XX0
H'0000XX0
Trc Trr Trc
REF
Hi-Z
EMRS
Command
Issue Address


H'YYYYYYY
H'YYYYYYY
H'YYYYYYY
H'YYYYYYY
Trc Tmw Tnop Temw Tnop
MRS EMRS